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Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Author: Scott Smith

Publisher: Springer Nature

Published: 2022-06-01

Total Pages: 86

ISBN-13: 3031798007

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Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

Book Synopsis Designing Asynchronous Circuits using NULL Convention Logic (NCL) by : Scott Smith

Download or read book Designing Asynchronous Circuits using NULL Convention Logic (NCL) written by Scott Smith and published by Springer Nature. This book was released on 2022-06-01 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt: Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA

Author: Indira Priyadarshini Dugganapally

Publisher:

Published: 2009

Total Pages: 102

ISBN-13:

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"This Master's thesis outlines the design of a completely asynchronous Field Programmable Gate Array (FPGA) for implementing NULL Convention Logic (NCL) digital circuits. The proposed design uses four Configurable Logic Blocks (CLB), each of which in turn is designed using four Logic Elements (LE) to implement NCL logic function. Each LE can be configured to function as any one of the 27 fundamental NCL gates. A Logic Element is designed by concatenating a Look-Up-Table (LUT) with a pull-up pull-down transistor chain and a hysteresis loop. The interconnections and the switch box are designed using pass transistors and SRAM. In this thesis, a 4-input Look-Up Table (LUT) based 16-gate FPGA specifically for NCL circuits was designed and successfully programmed as a dual-rail non-pipelined 4-bit NCL register. The design was first created using the schematic capture, followed by layout or the physical level designs subsequent to successful simulation. The NCL FPGA is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process. The size of FPGAs is now more than 1 million equivalent gates, making them a viable alternative to custom design for all but the most complex processors. FPGAs are relatively low-cost and are reconfigurable, making them perfect for prototyping, as well as implementing the final design, especially for low volume production. To compete with this cheap, reconfigurable synchronous implementation, an NCL-specific FPGA is needed, such that NCL circuits can be implemented without necessitating a prohibitively expensive full-custom design"--Abstract, leaf iii.

Book Synopsis Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA by : Indira Priyadarshini Dugganapally

Download or read book Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA written by Indira Priyadarshini Dugganapally and published by . This book was released on 2009 with total page 102 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This Master's thesis outlines the design of a completely asynchronous Field Programmable Gate Array (FPGA) for implementing NULL Convention Logic (NCL) digital circuits. The proposed design uses four Configurable Logic Blocks (CLB), each of which in turn is designed using four Logic Elements (LE) to implement NCL logic function. Each LE can be configured to function as any one of the 27 fundamental NCL gates. A Logic Element is designed by concatenating a Look-Up-Table (LUT) with a pull-up pull-down transistor chain and a hysteresis loop. The interconnections and the switch box are designed using pass transistors and SRAM. In this thesis, a 4-input Look-Up Table (LUT) based 16-gate FPGA specifically for NCL circuits was designed and successfully programmed as a dual-rail non-pipelined 4-bit NCL register. The design was first created using the schematic capture, followed by layout or the physical level designs subsequent to successful simulation. The NCL FPGA is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process. The size of FPGAs is now more than 1 million equivalent gates, making them a viable alternative to custom design for all but the most complex processors. FPGAs are relatively low-cost and are reconfigurable, making them perfect for prototyping, as well as implementing the final design, especially for low volume production. To compete with this cheap, reconfigurable synchronous implementation, an NCL-specific FPGA is needed, such that NCL circuits can be implemented without necessitating a prohibitively expensive full-custom design"--Abstract, leaf iii.

Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

Author: Farhad Alibeygi Parsan

Publisher:

Published: 2014

Total Pages: 204

ISBN-13: 9781321358858

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Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL).

Book Synopsis Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures by : Farhad Alibeygi Parsan

Download or read book Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures written by Farhad Alibeygi Parsan and published by . This book was released on 2014 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt: Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL).

An Asynchronous FPGA for NULL Convention Logic Circuits

Author: Arun Swaminathan Balasubramanian

Publisher:

Published: 2005

Total Pages: 154

ISBN-13:

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"This Master's thesis is intended to familiarize the reader with the asynchronous delay-insensitive NULL convention Logic (NCL) paradigm and illustrate the design of a completely asynchronous Field Programmable Gate Array (FPGA) for NULL Convention Logic circuits. Mentor Graphics Design Automation tools such as Design Architect and Accusim II were extensively used in creating this design"--Introduction, leaf 1.

Book Synopsis An Asynchronous FPGA for NULL Convention Logic Circuits by : Arun Swaminathan Balasubramanian

Download or read book An Asynchronous FPGA for NULL Convention Logic Circuits written by Arun Swaminathan Balasubramanian and published by . This book was released on 2005 with total page 154 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This Master's thesis is intended to familiarize the reader with the asynchronous delay-insensitive NULL convention Logic (NCL) paradigm and illustrate the design of a completely asynchronous Field Programmable Gate Array (FPGA) for NULL Convention Logic circuits. Mentor Graphics Design Automation tools such as Design Architect and Accusim II were extensively used in creating this design"--Introduction, leaf 1.

Ultra-low Power and Radiation Hardened Asynchronous Circuit Design

Author: Liang Zhou

Publisher:

Published: 2012

Total Pages: 122

ISBN-13: 9781267310583

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This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation. This dissertation also develops an architecture that allows NCL circuits to recover from a Single Event Upset (SEU) or Single Event Latchup (SEL) fault without any data loss. Finally, an accurate throughput derivation formula for pipelined NCL circuits was developed, which can be used for static timing analysis.

Book Synopsis Ultra-low Power and Radiation Hardened Asynchronous Circuit Design by : Liang Zhou

Download or read book Ultra-low Power and Radiation Hardened Asynchronous Circuit Design written by Liang Zhou and published by . This book was released on 2012 with total page 122 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation. This dissertation also develops an architecture that allows NCL circuits to recover from a Single Event Upset (SEU) or Single Event Latchup (SEL) fault without any data loss. Finally, an accurate throughput derivation formula for pipelined NCL circuits was developed, which can be used for static timing analysis.

Asynchronous Circuit Applications

Author: Jia Di

Publisher: Materials, Circuits and Device

Published: 2020-01-02

Total Pages: 369

ISBN-13: 1785618172

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This book introduces a wide range of existing and potential applications for asynchronous circuits, each accompanied with the corresponding circuit design theory, sample circuit implementations, results, and analysis.

Book Synopsis Asynchronous Circuit Applications by : Jia Di

Download or read book Asynchronous Circuit Applications written by Jia Di and published by Materials, Circuits and Device. This book was released on 2020-01-02 with total page 369 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces a wide range of existing and potential applications for asynchronous circuits, each accompanied with the corresponding circuit design theory, sample circuit implementations, results, and analysis.

Design and Characterization of Asynchronous Delay-insensitive Arithemetic Components Using NULL Conventional Logic

Author: Satish Kumar Bandapati

Publisher:

Published: 2003

Total Pages: 134

ISBN-13:

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"This thesis focuses on design and characterization of arithemetic circuits, such as multipliers and ALUs, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to aid in the integration of asynchronous design paradigms, like NCL, into the semiconductor design industry."--Abstract, p. iii.

Book Synopsis Design and Characterization of Asynchronous Delay-insensitive Arithemetic Components Using NULL Conventional Logic by : Satish Kumar Bandapati

Download or read book Design and Characterization of Asynchronous Delay-insensitive Arithemetic Components Using NULL Conventional Logic written by Satish Kumar Bandapati and published by . This book was released on 2003 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This thesis focuses on design and characterization of arithemetic circuits, such as multipliers and ALUs, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to aid in the integration of asynchronous design paradigms, like NCL, into the semiconductor design industry."--Abstract, p. iii.

CAD Tool Design for NCL and MTNCL Asynchronous Circuits

Author: Vijay Mani Pillai

Publisher:

Published: 2013

Total Pages: 104

ISBN-13: 9781303117220

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This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit x 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU).

Book Synopsis CAD Tool Design for NCL and MTNCL Asynchronous Circuits by : Vijay Mani Pillai

Download or read book CAD Tool Design for NCL and MTNCL Asynchronous Circuits written by Vijay Mani Pillai and published by . This book was released on 2013 with total page 104 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit x 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU).

Principles of Asynchronous Circuit Design

Author: Jens Sparsø

Publisher: Springer Science & Business Media

Published: 2001-12-31

Total Pages: 372

ISBN-13: 9780792376132

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Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

Book Synopsis Principles of Asynchronous Circuit Design by : Jens Sparsø

Download or read book Principles of Asynchronous Circuit Design written by Jens Sparsø and published by Springer Science & Business Media. This book was released on 2001-12-31 with total page 372 pages. Available in PDF, EPUB and Kindle. Book excerpt: Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

Asynchronous 3D (Async3D)

Author: Francis Corpuz Sabado II

Publisher:

Published: 2017

Total Pages: 178

ISBN-13:

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This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology.

Book Synopsis Asynchronous 3D (Async3D) by : Francis Corpuz Sabado II

Download or read book Asynchronous 3D (Async3D) written by Francis Corpuz Sabado II and published by . This book was released on 2017 with total page 178 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology.