Author: Gürsel Düzenli

Publisher:

Published: 2003

Total Pages:

ISBN-13:

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The down-scaling of device dimensions in CMOS technology will improve performance and packing density for VLSI (Very Large Scale Integration) circuits, but it will negatively effect the quaIity of the circuits. Integrated circuits (ICs) are basically classified according to the electrical function they perform. Integrated circuits performing nominally the same function, however, do not necessarily perform it equally well. The concept of quality is used to express how well the required function is performed. An operational amplifier is of higher quality İf it has a higher gain, wider frequency bandwidth, etc. These characteristics can be regarded as conformance figures. The conformance is, however, only one side of the quality. On the other side is the issue of how Iong the device or circuit will exhibit the initial performance figures. The concept of reliabillty is used to express this time dimension of the quality . Measurement and presentation of the conformance figures are straightforward; any conformance parameter can be measured directly and its value expressed. The situation is, however, different from determination and presentation of the reliability. The reliabilİty depends, in principle, on application conditions, which means it is not possible to establish an exact and unique reliability figure for a given device or IC. In addition, the reliability, determination itself, regardless of the application conditions used, cannot be made by direct measurements. This is mainly because of practical constraints. Theoretically, it is possible to determine the mean time to failure directly if a corresponding number of device or ICs are exposed to working conditions and times to failure of each of them are recorded. This is, however, practically meaningless; such a test would last for tens of years, and by the time the data are collected nobody would be interested in them. That is why accelerated tests have to be applied to obtain the results in a reasonable time of 1 or 2 months. The failures in ICs can be classified in at least three different ways: according to failure modes, according to failure mechanisms, and according to failure causes. The failure mode is the observed result of a failure, such as an open circuit, short circuit, or parameter degradation. The failure mechanism is the phyical, chemical, or other process that results in a failure. Finally , the failure cause is a circumstance during design, production, testing, or operation that initates or contributes to a failure mechanism. The focus of this study is the modeling of parameter degradation reliability of p- MOS and n-MOS transistors due to the hot-carriers under analog operation. Hot- carrier failure cause can initiate the electron/holetrapping/generation and/or interface trap creation mechanism leading to changes of oxide charge and trap densities during device operation. A lot of efforts have been devoted to study the mechanisms due to the hot-carrier and modeling the device degradation due to these effects. However , these modelings are often performed on digital applications. Analog applications differ from digital ones by a number of points. Analog circuit reliability prediction has to take analog circuit design variables such as channel length, biasing conditions, and circuit topography into consideration. In order to achieve highest possible speed, smallest area and smallest power consumption usually L=Lmin are chosen for digital applications. However, for nearly all-analog applications this choice is inadequate. In order to improve matching and noise behavior, channel lengths usually need to be chosen several times Lmin. For those greater lengths also the small-signal parameters especially the drain conductance, are largely improved. However, because analog circuits usually use long-channel devices, the influence of hot-carrier effects on analog circuit performance has been believed to be minimal and, as a result, has been mostly overlooked. Therefore, the most important device parameters in these two application fields do not coincide. For example, power supply scaling for analog circuİts will not likely be as aggressive as for digital circuits, because submicron devices are necessary for high speed applications. However , the operation of analog circuits is sensitive to device parameter variations. Furthermore, device parameter variations depend on the specific application of a given analog circuit. The proposed models combines the advantages of the parameter fitting method and so-called AId model. The essence of the model is the translation of the physical W,mechanisms leading to degradation into the MOSFET model equations correct place via an empirical description. Because of the correct place of the empirical description in the MOSFET model equations the parameter extraction will be as simple as that of the so-called LlIo model. The empirical description was found from different degradations and fresh devices, so the accuracy is as high as that of the parameter fitting method. Furthermore, the general structure of the empirical description is independent of the process technology. Therefore, it does not impose a much higher requirement on device engineer . Another important feature of the proposed models is the prediction of the device lifetime at real life. This is an important feature because most of the developed degradation models are not able to predict the device lifetime. Therefore, several extrapolation laws to calculate the Iifetime have been developed. But, most of the developed lifetime prediction models are developed for digital applications. However, when the same lifetime prediction models are applied to analog applications, gross lifetime prediction error results. This is because the stress conditions are totally different in analog applications compared to digital applications. The proposed model includes a hot-carrier degradation model and a lifetime prediction model as a single model suitable for analog applications. The accuracy of the presented models has been verified with experimental data.

Download or read book Development of Mosfet Models Suitable for Simulation of Analog CMOS Circuits After Hot-carrier Stress written by Gürsel Düzenli and published by . This book was released on 2003 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The down-scaling of device dimensions in CMOS technology will improve performance and packing density for VLSI (Very Large Scale Integration) circuits, but it will negatively effect the quaIity of the circuits. Integrated circuits (ICs) are basically classified according to the electrical function they perform. Integrated circuits performing nominally the same function, however, do not necessarily perform it equally well. The concept of quality is used to express how well the required function is performed. An operational amplifier is of higher quality İf it has a higher gain, wider frequency bandwidth, etc. These characteristics can be regarded as conformance figures. The conformance is, however, only one side of the quality. On the other side is the issue of how Iong the device or circuit will exhibit the initial performance figures. The concept of reliabillty is used to express this time dimension of the quality . Measurement and presentation of the conformance figures are straightforward; any conformance parameter can be measured directly and its value expressed. The situation is, however, different from determination and presentation of the reliability. The reliabilİty depends, in principle, on application conditions, which means it is not possible to establish an exact and unique reliability figure for a given device or IC. In addition, the reliability, determination itself, regardless of the application conditions used, cannot be made by direct measurements. This is mainly because of practical constraints. Theoretically, it is possible to determine the mean time to failure directly if a corresponding number of device or ICs are exposed to working conditions and times to failure of each of them are recorded. This is, however, practically meaningless; such a test would last for tens of years, and by the time the data are collected nobody would be interested in them. That is why accelerated tests have to be applied to obtain the results in a reasonable time of 1 or 2 months. The failures in ICs can be classified in at least three different ways: according to failure modes, according to failure mechanisms, and according to failure causes. The failure mode is the observed result of a failure, such as an open circuit, short circuit, or parameter degradation. The failure mechanism is the phyical, chemical, or other process that results in a failure. Finally , the failure cause is a circumstance during design, production, testing, or operation that initates or contributes to a failure mechanism. The focus of this study is the modeling of parameter degradation reliability of p- MOS and n-MOS transistors due to the hot-carriers under analog operation. Hot- carrier failure cause can initiate the electron/holetrapping/generation and/or interface trap creation mechanism leading to changes of oxide charge and trap densities during device operation. A lot of efforts have been devoted to study the mechanisms due to the hot-carrier and modeling the device degradation due to these effects. However , these modelings are often performed on digital applications. Analog applications differ from digital ones by a number of points. Analog circuit reliability prediction has to take analog circuit design variables such as channel length, biasing conditions, and circuit topography into consideration. In order to achieve highest possible speed, smallest area and smallest power consumption usually L=Lmin are chosen for digital applications. However, for nearly all-analog applications this choice is inadequate. In order to improve matching and noise behavior, channel lengths usually need to be chosen several times Lmin. For those greater lengths also the small-signal parameters especially the drain conductance, are largely improved. However, because analog circuits usually use long-channel devices, the influence of hot-carrier effects on analog circuit performance has been believed to be minimal and, as a result, has been mostly overlooked. Therefore, the most important device parameters in these two application fields do not coincide. For example, power supply scaling for analog circuİts will not likely be as aggressive as for digital circuits, because submicron devices are necessary for high speed applications. However , the operation of analog circuits is sensitive to device parameter variations. Furthermore, device parameter variations depend on the specific application of a given analog circuit. The proposed models combines the advantages of the parameter fitting method and so-called AId model. The essence of the model is the translation of the physical W,mechanisms leading to degradation into the MOSFET model equations correct place via an empirical description. Because of the correct place of the empirical description in the MOSFET model equations the parameter extraction will be as simple as that of the so-called LlIo model. The empirical description was found from different degradations and fresh devices, so the accuracy is as high as that of the parameter fitting method. Furthermore, the general structure of the empirical description is independent of the process technology. Therefore, it does not impose a much higher requirement on device engineer . Another important feature of the proposed models is the prediction of the device lifetime at real life. This is an important feature because most of the developed degradation models are not able to predict the device lifetime. Therefore, several extrapolation laws to calculate the Iifetime have been developed. But, most of the developed lifetime prediction models are developed for digital applications. However, when the same lifetime prediction models are applied to analog applications, gross lifetime prediction error results. This is because the stress conditions are totally different in analog applications compared to digital applications. The proposed model includes a hot-carrier degradation model and a lifetime prediction model as a single model suitable for analog applications. The accuracy of the presented models has been verified with experimental data.