Hot-Carrier Reliability of MOS VLSI Circuits

Hot-Carrier Reliability of MOS VLSI Circuits

Author: Yusuf Leblebici

Publisher: Springer Science & Business Media

Published: 2012-12-06

Total Pages: 223

ISBN-13: 1461532507

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As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.


Book Synopsis Hot-Carrier Reliability of MOS VLSI Circuits by : Yusuf Leblebici

Download or read book Hot-Carrier Reliability of MOS VLSI Circuits written by Yusuf Leblebici and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 223 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.


VLSI Design for Reliability-Hot Carrier Effects

VLSI Design for Reliability-Hot Carrier Effects

Author:

Publisher:

Published: 1993

Total Pages: 76

ISBN-13:

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This report describes the accomplishments during the contract period (June 28, to June 27, 1992) on the computer aided analysis of CMOS device and circuit degradation due to hot-carrier effects. The task involved four subtasks: (1) simulation of gate oxide degradation during long-term circuit operation; (2) determination of overall circuit performance after hot-electron stress; (3) probabilistic timing approach to hot-carrier-effect estimation; (4) parametric macromodeling of hot-carrier-induced degradation in MOS VLSI circuits. The first two parts are continued subtasks while the latter two are new subtasks. In order to simulate the reliability of MOS circuits, both the detailed model and the macromodel are used; the detailed model is used for accurate analysis of small circuits and the macromodel is used for very large circuits for computational efficiency. Since the hot-carrier-induced aging of MOS circuits is input-pattern dependent, an important task is to develop a computationally efficient probabilistic timing approach to hot-carrier-effect estimation without resorting to the Monte Carlo simulation. We have developed a new probabilistic approach that accounts for cumulative effects of all input waveform combinations in a single run. VLSI reliability, Hot-carrier effects, Computer aided design.


Book Synopsis VLSI Design for Reliability-Hot Carrier Effects by :

Download or read book VLSI Design for Reliability-Hot Carrier Effects written by and published by . This book was released on 1993 with total page 76 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report describes the accomplishments during the contract period (June 28, to June 27, 1992) on the computer aided analysis of CMOS device and circuit degradation due to hot-carrier effects. The task involved four subtasks: (1) simulation of gate oxide degradation during long-term circuit operation; (2) determination of overall circuit performance after hot-electron stress; (3) probabilistic timing approach to hot-carrier-effect estimation; (4) parametric macromodeling of hot-carrier-induced degradation in MOS VLSI circuits. The first two parts are continued subtasks while the latter two are new subtasks. In order to simulate the reliability of MOS circuits, both the detailed model and the macromodel are used; the detailed model is used for accurate analysis of small circuits and the macromodel is used for very large circuits for computational efficiency. Since the hot-carrier-induced aging of MOS circuits is input-pattern dependent, an important task is to develop a computationally efficient probabilistic timing approach to hot-carrier-effect estimation without resorting to the Monte Carlo simulation. We have developed a new probabilistic approach that accounts for cumulative effects of all input waveform combinations in a single run. VLSI reliability, Hot-carrier effects, Computer aided design.


Hot Carrier Design Considerations for MOS Devices and Circuits

Hot Carrier Design Considerations for MOS Devices and Circuits

Author: Cheng Wang

Publisher: Springer Science & Business Media

Published: 2012-12-06

Total Pages: 345

ISBN-13: 1468485474

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As device dimensions decrease, hot-carrier effects, which are due mainly to the presence of a high electric field inside the device, are becoming a major design concern. On the one hand, the detrimental effects-such as transconductance degradation and threshold shift-need to be minimized or, if possible, avoided altogether. On the other hand, performance such as the programming efficiency of nonvolatile memories or the carrier velocity inside the devices-need to be maintained or improved through the use of submicron technologies, even in the presence of a reduced power supply. As a result, one of the major challenges facing MOS design engineers today is to harness the hot-carrier effects so that, without sacrificing product performance, degradation can be kept to a minimum and a reli able design obtained. To accomplish this, the physical mechanisms re sponsible for the degradations should first be experimentally identified and characterized. With adequate models thus obtained, steps can be taken to optimize the design, so that an adequate level of quality assur ance in device or circuit performance can be achieved. This book ad dresses these hot-carrier design issues for MOS devices and circuits, and is used primarily as a professional guide for process development engi neers, device engineers, and circuit designers who are interested in the latest developments in hot-carrier degradation modeling and hot-carrier reliability design techniques. It may also be considered as a reference book for graduate students who have some research interests in this excit ing, yet sometime controversial, field.


Book Synopsis Hot Carrier Design Considerations for MOS Devices and Circuits by : Cheng Wang

Download or read book Hot Carrier Design Considerations for MOS Devices and Circuits written by Cheng Wang and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 345 pages. Available in PDF, EPUB and Kindle. Book excerpt: As device dimensions decrease, hot-carrier effects, which are due mainly to the presence of a high electric field inside the device, are becoming a major design concern. On the one hand, the detrimental effects-such as transconductance degradation and threshold shift-need to be minimized or, if possible, avoided altogether. On the other hand, performance such as the programming efficiency of nonvolatile memories or the carrier velocity inside the devices-need to be maintained or improved through the use of submicron technologies, even in the presence of a reduced power supply. As a result, one of the major challenges facing MOS design engineers today is to harness the hot-carrier effects so that, without sacrificing product performance, degradation can be kept to a minimum and a reli able design obtained. To accomplish this, the physical mechanisms re sponsible for the degradations should first be experimentally identified and characterized. With adequate models thus obtained, steps can be taken to optimize the design, so that an adequate level of quality assur ance in device or circuit performance can be achieved. This book ad dresses these hot-carrier design issues for MOS devices and circuits, and is used primarily as a professional guide for process development engi neers, device engineers, and circuit designers who are interested in the latest developments in hot-carrier degradation modeling and hot-carrier reliability design techniques. It may also be considered as a reference book for graduate students who have some research interests in this excit ing, yet sometime controversial, field.


Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits

Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits

Author: Weishi Sun

Publisher:

Published: 1992

Total Pages: 142

ISBN-13:

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Book Synopsis Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits by : Weishi Sun

Download or read book Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits written by Weishi Sun and published by . This book was released on 1992 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt:


Hot-Carrier Effects in MOS Devices

Hot-Carrier Effects in MOS Devices

Author: Eiji Takeda

Publisher: Elsevier

Published: 1995-11-28

Total Pages: 329

ISBN-13: 0080926223

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The exploding number of uses for ultrafast, ultrasmall integrated circuits has increased the importance of hot-carrier effects in manufacturing as well as for other technological applications. They are rapidly movingout of the research lab and into the real world. This book is derived from Dr. Takedas book in Japanese, Hot-Carrier Effects, (published in 1987 by Nikkei Business Publishers). However, the new book is much more than a translation. Takedas original work was a starting point for developing this much more complete and fundamental text on this increasingly important topic. The new work encompasses not only all the latest research and discoveries made in the fast-paced area of hot carriers, but also includes the basics of MOS devices, and the practical considerations related to hot carriers. Chapter one itself is a comprehensive review of MOS device physics which allows a reader with little background in MOS devices to pick up a sufficient amount of information to be able to follow the rest of the book The book is written to allow the reader to learn about MOS Device Reliability in a relatively short amount of time, making the texts detailed treatment of hot-carrier effects especially useful and instructive to both researchers and others with varyingamounts of experience in the field The logical organization of the book begins by discussing known principles, then progresses to empirical information and, finally, to practical solutions Provides the most complete review of device degradation mechanisms as well as drain engineering methods Contains the most extensive reference list on the subject


Book Synopsis Hot-Carrier Effects in MOS Devices by : Eiji Takeda

Download or read book Hot-Carrier Effects in MOS Devices written by Eiji Takeda and published by Elsevier. This book was released on 1995-11-28 with total page 329 pages. Available in PDF, EPUB and Kindle. Book excerpt: The exploding number of uses for ultrafast, ultrasmall integrated circuits has increased the importance of hot-carrier effects in manufacturing as well as for other technological applications. They are rapidly movingout of the research lab and into the real world. This book is derived from Dr. Takedas book in Japanese, Hot-Carrier Effects, (published in 1987 by Nikkei Business Publishers). However, the new book is much more than a translation. Takedas original work was a starting point for developing this much more complete and fundamental text on this increasingly important topic. The new work encompasses not only all the latest research and discoveries made in the fast-paced area of hot carriers, but also includes the basics of MOS devices, and the practical considerations related to hot carriers. Chapter one itself is a comprehensive review of MOS device physics which allows a reader with little background in MOS devices to pick up a sufficient amount of information to be able to follow the rest of the book The book is written to allow the reader to learn about MOS Device Reliability in a relatively short amount of time, making the texts detailed treatment of hot-carrier effects especially useful and instructive to both researchers and others with varyingamounts of experience in the field The logical organization of the book begins by discussing known principles, then progresses to empirical information and, finally, to practical solutions Provides the most complete review of device degradation mechanisms as well as drain engineering methods Contains the most extensive reference list on the subject


Hot-carrier Reliability of CMOS Integrated Circuits

Hot-carrier Reliability of CMOS Integrated Circuits

Author: Jone Fang Chen

Publisher:

Published: 1998

Total Pages: 242

ISBN-13:

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Book Synopsis Hot-carrier Reliability of CMOS Integrated Circuits by : Jone Fang Chen

Download or read book Hot-carrier Reliability of CMOS Integrated Circuits written by Jone Fang Chen and published by . This book was released on 1998 with total page 242 pages. Available in PDF, EPUB and Kindle. Book excerpt:


Prototype Rule-Based Reliability Analysis for VLSI Circuit Design

Prototype Rule-Based Reliability Analysis for VLSI Circuit Design

Author:

Publisher:

Published: 1994

Total Pages: 82

ISBN-13:

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This report describes the development and application of parametric and geometry based macro-models of hot-carrier induced dynamic degradation in MOS VLSI circuits. Previously, a simulation based approach has been used for reliability analysis, but this is inefficient for reliability assessment of very large scale integrated circuits. Geometry-based macro-models for hot-carrier reliability estimation have been developed. The macro-models express hot-carrier damage as functions of designable parameters such as transistor size (W), output loading capacitance (C1) and the input signal slew rate (a). A prototype rule- based reliability diagnosis tool, iRULE, has been developed. This tool uses the macro-models for designing hot-carrier resistant circuits without the need for transient reliability simulations. This provides the ability to analyze very large circuits with more than one million transistors on a workstation in a short amount of time. This report also describes a fast timing reliability simulation tool, ILLIADS-R, that can accurately estimate hot-carrier degradation while providing several orders of magnitude speed up over traditional transistor-level circuit simulators. Reliability, Hot-carrier degradation, VLSI CMOS Circuits, Simulation.


Book Synopsis Prototype Rule-Based Reliability Analysis for VLSI Circuit Design by :

Download or read book Prototype Rule-Based Reliability Analysis for VLSI Circuit Design written by and published by . This book was released on 1994 with total page 82 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report describes the development and application of parametric and geometry based macro-models of hot-carrier induced dynamic degradation in MOS VLSI circuits. Previously, a simulation based approach has been used for reliability analysis, but this is inefficient for reliability assessment of very large scale integrated circuits. Geometry-based macro-models for hot-carrier reliability estimation have been developed. The macro-models express hot-carrier damage as functions of designable parameters such as transistor size (W), output loading capacitance (C1) and the input signal slew rate (a). A prototype rule- based reliability diagnosis tool, iRULE, has been developed. This tool uses the macro-models for designing hot-carrier resistant circuits without the need for transient reliability simulations. This provides the ability to analyze very large circuits with more than one million transistors on a workstation in a short amount of time. This report also describes a fast timing reliability simulation tool, ILLIADS-R, that can accurately estimate hot-carrier degradation while providing several orders of magnitude speed up over traditional transistor-level circuit simulators. Reliability, Hot-carrier degradation, VLSI CMOS Circuits, Simulation.


Hot-carrier Reliability Assessment in CMOS Digital Integrated Circuits

Hot-carrier Reliability Assessment in CMOS Digital Integrated Circuits

Author: Wenjie Jiang

Publisher:

Published: 1998

Total Pages: 218

ISBN-13:

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Book Synopsis Hot-carrier Reliability Assessment in CMOS Digital Integrated Circuits by : Wenjie Jiang

Download or read book Hot-carrier Reliability Assessment in CMOS Digital Integrated Circuits written by Wenjie Jiang and published by . This book was released on 1998 with total page 218 pages. Available in PDF, EPUB and Kindle. Book excerpt:


Hot-carrier Reliability of Integrated Circuits

Hot-carrier Reliability of Integrated Circuits

Author: Khandker Nazrul Quader

Publisher:

Published: 1993

Total Pages: 368

ISBN-13:

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Book Synopsis Hot-carrier Reliability of Integrated Circuits by : Khandker Nazrul Quader

Download or read book Hot-carrier Reliability of Integrated Circuits written by Khandker Nazrul Quader and published by . This book was released on 1993 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt:


Hot-carrier Reliability Evaluation for CMOS Devices and Circuits

Hot-carrier Reliability Evaluation for CMOS Devices and Circuits

Author: Vei-Han Chan

Publisher:

Published: 1995

Total Pages: 148

ISBN-13:

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Book Synopsis Hot-carrier Reliability Evaluation for CMOS Devices and Circuits by : Vei-Han Chan

Download or read book Hot-carrier Reliability Evaluation for CMOS Devices and Circuits written by Vei-Han Chan and published by . This book was released on 1995 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: